Power MOSFETs are generally used as switches to control the flow of power to an instrument such as a portable computer. FIG. 1A shows a schematic diagram of a power MOSFET 10 having a gate G', a source S' and a drain D' which is configured in a typical way with a buffer amplifier 12 connected to gate G'. MOSFET 10 also has a body B which is shorted to its source G' to prevent the parasitic bipolar transistor within MOSFET 10 from turning on. Also shown in FIG. 1A is a parasitic diode 11 with its anode connected to the source/body of MOSFET 10 and its cathode connected to the drain D'. Since MOSFET 10 is an N-channel MOSFET, buffer amplifier 12 supplies a positive gate drive voltage V.sub.CC to turn MOSFET 10 on or grounds gate G' to turn MOSFET 10 off. MOSFET 10 could also be a P-channel MOSFET in which case the voltage V.sub.CC necessary to turn MOSFET 10 on would be negative.
The source S', body B and drain D' are formed in a semiconductor material such as silicon. Gate G' is formed of a conductive material such as polycrystalline silicon and is separated from the semiconductor material by an insulating layer which is typically silicon dioxide. In normal operation, to protect the gate oxide layer, V.sub.CC is set not to exceed a maximum gate-to-source voltage V.sub.GS (max). If V.sub.CC exceeds V.sub.GS (max), the gate oxide layer may be ruptured or otherwise damaged, and MOSFET 10 may be permanently destroyed.
V.sub.GS (max) is generally determined by the thickness (X.sub.OX) of the gate oxide layer. As a rule, the gate oxide layer will rupture when V.sub.GS exceeds about 10 to 12 megavolts (MV) times the thickness X.sub.OX expressed in centimeters. When the oxide layer is thicker (e.g., 300 .ANG. thick), this factor actually becomes lower (e.g., 8 MV/cm) because there is less leakage current as a result of tunneling between the gate and the semiconductor material. Tunneling does not damage the gate oxide layer. Thus, allowing a safety factor of 50%, V.sub.GS should normally be kept below 5 or 6 MV/cm multiplied by X.sub.OX, or below 4 MV/cm multiplied by X.sub.OX when the gate oxide layer is thick. For example, a 175 .ANG. thick oxide layer will rupture at 16 V to 18 V and V.sub.GS (max) is around 8 V or 9 V, whereas a 300 .ANG. thick oxide layer will rupture at about 24 V and V.sub.GS (max) is about 12 V.
If the gate voltage V.sub.GS exceeds the higher rupture voltage, the device will be destroyed instantly. If V.sub.GS is in the range between the rupture voltage and V.sub.GS (max), the device may not be destroyed instantly, but it may be partially damaged. Even if the gate voltage returns to a safe level below V.sub.GS (max), this latent damage may eventually cause the gate oxide layer to wear out, and the device may later become inoperative. For this reason, MOSFETs which have been exposed to gate voltages in the interval between V.sub.GS (max) and the rupture voltage are sometimes referred to as "walking wounded".
Voltages resulting from electrostatic discharges (ESD) present a different situation. Since ESD voltages are very high but often of very short duration, they are sometimes modeled as shown in FIG. 1B as a capacitor C.sub.esd charged to thousands of volts (e.g., more than 2 kV as shown in FIG. 1B) in series with resistor R.sub.esd. Depending on the relative sizes of C.sub.esd and the gate capacitance of MOSFET 10 and the size of R.sub.esd, MOSFET 10 may be able to survive the ESD pulse with no damage if C.sub.esd is small (i.e., the ESD pulse is short-lived) and R.sub.esd and the gate capacitance large. In this situation the flow of current into the gate is limited by R.sub.esd, preventing the rate of rise of V.sub.GS to a dangerous level before the energy associated with the ESD pulse can be dissipated. In essence, the C.sub.esd, R.sub.esd and the gate capacitance form a voltage divider circuit.
ESD pulses or other high voltages on the drain are not generally a problem because depletion spreading in the semiconductor material absorbs a significant part of the voltage between the drain and gate and thus the gate oxide layer is not exposed to the entire drain voltage.
FIG. 2 shows a graph of V.sub.GS applied to a MOSFET in several situations. The device could be designed for a normal gate drive of 5 V, and the rupture voltage could be 8 V. The overvoltage conditions of about 12 V oCCur when V.sub.GS exceeds 8 V in either a positive or negative direction. These conditions could arise from ringing voltages on a battery charger or when someone plugs in the wrong battery charger. Because these voltages are of a relatively long duration, they can burn up any diodes that are used to clamp the gate voltage. Finally, the device could be subjected to an ESD pulse of plus or minus 2000 V. ESD pulses have a very short duration, however, so the diode clamps may be able to survive them.
FIGS. 3A and 3B are circuit diagrams of a lithium ion battery pack 30 that includes voltage clamps 31 and 33 to protect the gates of MOSFETs 32 and 34, respectively. MOSFETs 32 and 34 switch the current from a lithium ion battery 35 and are connected in series in a drain-to-drain configuration. The gate voltages of the MOSFETs 32 and 34 are controlled by a control IC 36. Voltage clamps 31 and 33 are shown as consisting of a single pair of back-to-back diodes. FIG. 3A shows an ESD pulse of 12,000 V applied to the terminals of the battery pack 30. If the devices are on when the ESD pulse oCCurs, the 12,000 V pulse is distributed in some manner among the devices in battery pack 30, and some portion will appear between the gate and source terminals of MOSFETs 32 and 34.
If a DC overvoltage of 12 V is applied, however, as shown in FIG. 3B, the control IC 36 may be able to survive and pass the entire 12 V on to the gates of MOSFETs 32 and 34. Assuming, for example, that voltage clamps 31 and 33 are designed to break down at 8 V, which is the rated operating voltage of MOSFETs 32 and 34, then the diodes within voltage clamps 31 and 33 will most likely conduct too much current and will burn up.
The above-referenced Application No. 09/001,768 describes a number of diode configurations that can be used as voltage clamps to protect the gate oxide layer.